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概要

IEEE、ACM、IEICEなどの主要ジャーナル・国際会議を中心に、査読付き論文を60件以上発表しています。研究分野は、ディペンダブルVLSIテスト、車載機能安全、チップレットシステム、AIチップ信頼性、セキュア設計です。

Functional Fault Impact Probability Prediction using Spatio-Temporal Graph Convolutional Network
Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Ruijun Ma, Tianming Ni, Xiaoqing Wen, Hiroshi Takahashi
ACM Transactions on Design Automation of Electronic Systems, Vol. 31, No. 5, Article 102, September 2026
DOI
A lightweight general PUF framework for resisting machine learning attacks
Tianming Ni, Fei Li, Zhengfeng Huang, Aibin Yan, Senling Wang, Xiaoqing Wen, Mu Nie, Jingchang Bian
Integration, Vol. 104, September 2025, 102459
DOI
SASL-JTAG+: An Enhanced Lightweight and Secure JTAG Authentication Mechanism for IoT Systems
Hisashi Okamoto, Shaoqi Wei, Senling Wang, et al.
Journal of Communications, Vol. 20, No. 2, 2025, pp. 214-220
DOI
Test Point Insertion for Multi-Cycle Power-On Self-Test
Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
ACM Transactions on Design Automation of Electronic Systems, Vol. 28, No. 3, Article 46, 2023
DOI
Automotive Functional Safety Assurance by POST with Sequential Observation
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
IEEE Design and Test Magazine, Vol. 35, No. 3, 2018
DOI

Software-Defined Secure Island for Testing Chiplet Systems
IEEE 34th Asian Test Symposium (ATS), 2025
LLM-Design Platform for Thermal-Failure-Aware 3D Chiplet Layout
IEEE 34th Asian Test Symposium (ATS), 2025
A Lightweight and Secure One-time Authentication Protocol for MQTT
IEEE/IEIE ICCE-Asia, 2025
Binary Splitting Test Generation for Pattern Matching Accelerator
ICECC2025

Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs
ITC-Asia, 2024
Deep-BMNN: Implementing Sparse Binary Neural Networks in Memory-Based Reconfigurable Processor
ITC-CSCC, 2024
SASL-JTAG: A Light-Weight Dependable JTAG
IEEE DFTS, 2023

Studies on Test Application at Field Test and Low Power Logic-BIST
博士論文, 九州工業大学, 2014年3月
HDL Handle

Three Dimensional Integration of Semiconductors
分担執筆（Chapter 8）, Springer, 2015

基礎情報科学
分担執筆（Chapter 3）, 学術図書出版社, 2024